RF and Microwave Frequency Synthesizers are used in many applications including terrestrial communications, satellite communications, electronic warfare and countermeasures, and in instrumentation and systems testing, including in medical and nuclear research. In many of these systems there is a need for high stability signals with high signal purity and the ability to modulate the signals according to various modulation schemes, and to vary the frequencies often over multiple octave frequencies at high switching speeds, all at the lowest possible cost. The signal instabilities are a combination of amplitude and frequency (or phase) instabilities. The latter is often called Phase Noise, and is often a limiting factor in the performance of many systems.
Traditionally, frequency synthesis has been performed using Phase Locked Loops (PLLs) or Direct Digital Synthesis (DDS), and sometimes a combination of both. In both cases, a very stable Reference Oscillator (RO), often a Temperature controlled Crystal Oscillator (TCXO) or an Oven Controlled Crystal Oscillator (OCXO) usually operating at some frequency between 10 MHz and 100 MHz or more with excellent stability and Phase Noise characteristics, is used to provide the reference signal which forms the basis of the synthesized output. The PLL uses a tunable Voltage Controlled Oscillator (VCO) whose output is divided by a loop divider and in a feedback loop, locked to the VCXO or TCXO. A typical configuration is shown in FIG. 1, which is described in greater detail in the next section. The DDS uses the TCXO or VCXO as an accurate clock to generate a time function that approximates the sinusoidal output of an oscillator in a series of steps.
Current State of the Art PLLs such as the one shown in FIG. 1, divide the VCO frequency (Fvco/N) until it equals the RO frequency. Here N is not necessarily an integer. For example, with a 10 MHz RO and a 8567.3 MHz VCO, the value of N would be 856.73. The loop is closed via a low pass filter (LPF) that takes the difference between the RO and Fvco/N, filters it, and uses the output to fine-tune the VCO. Within the bandwidth of the PLL, which is mostly (but not totally) defined by the LPF, the phase noise of Fvco/N will track the phase noise of the RO so long as the loop gain is sufficiently large. The problem is that by dividing the VCO frequency by N, the magnitude of the phase noise is also reduced by a factor of N, i.e., 20 logN dB. The VCO phase noise will therefore be 20 logN worse than the RO within the loop bandwidth, and have the same characteristics as a free running VCO outside the loop bandwidth.
While this approach often gives meaningful and sufficient reduction in phase noise for use in many systems, in many other systems it does not. Also, achieving non-integer values of N requires techniques that result in spurious sidebands that are generated and often cannot be suppressed. At the same time DDS technology has not progressed to the extent of providing a usable alternative at 5 GHz and above at an acceptable cost or with usable integrated circuit chips. The present invention provides a meaningful solution to this performance divide by using an architecture that eliminates the “divide by N” issue in PLLs.